Project Info
| Name: | Walt | |
| Email: | walt@volersystems.com | |
| Phone: | 408-245-9844 ext 101 | |
| Company: | Voler Systems | |
| Address: | 1021 S. Wolfe Rd | |
| City, State, Zip: | Sunnyvale | |
| Website: | http://www.volersystems.com | |
| Project Name: | Design Verification | |
| Expertise: | Don't Know/Not Sure | |
| Description: | I am looking for someone to do design verification on an FPGA design using UVM (e/Specman language) on Cadence Incisive Unified Simulator (IUS)/ncsim. The person will write tests that will be used to verify the function of the FPGA. The work may run three to six months and starts as soon as possible. Familiarity with some of these tools is required. | |
| Date: | January 16, 2018 |