Project Info

Name:     Andrea Rivera
Phone:     4086937624
Company:     1994
Address:     800 hillsdale ave 713
City, State, Zip:     san jose
Project Name:     Design Verification Engineer
Expertise:     Don't Know/Not Sure
Description:     Job Function:

• Responsible for defining the Verification Methodology and plan for the development

• Develop SystemVerilog based UVM test bench environments

• Develop Coverage driven verification test plans, create directed and random testcases

• Develop test-suites for SoC and block level verification using latest tools and verification languages

• Perform the constraint assertion based verification

• Develop a co-simulation environment to verify between C/C++ models and RTL blocks.

• Manage the regression analysis


• BSEE with 8+ (or MSEE with 5+) years of related experience

• Experience in developing coverage driven Test-plans.

• Experience in writing Test-plans and creating directed and random testcases

• Experience in managing regression analysis

• Experience in High level Object Oriented Testbench environments such as UVM/VMM

• Strong SystemVerilog, Perl, Python and C/C++ Programming skills.

• A high level of pro-activity, initiative and problem solving

Work location : San Diego
Other Info:     Duration: 6 months, could be extended based on project
Date:     December 28, 2016