ECL ADVANTAGE, INC.

1022 E. Evelyn Ave., Suite 2P
Sunnyvale CA, 94086
Work Phone: 408-247-3254
tiddings@ieee.org

Very High Speed Digital Circuit Design & Signal Integrity
Electronic Engineering Design and Test. 20+ years in ATE (Automated Test Equipment), Test & Measurement, E-BEAM Control, Networks, & Biotech. Design of Control Systems, Pin Electronics, and robust High Speed Clock & Data Distribution Systems which work right the first time.

Architectures Created. Design Rules taught. Schematics Captured. PCB Layouts directed. Timing Analysis done. Power integrity reviewed. Signal Integrity reviewed. SPICE Modelling done. Debug before build via Simulation. System Integrations planned.


Prototypes designed, simulated, built, and tested.
PAST PROJECTS INCLUDE--
Design of the Pin Electronics, plus Master Clock Board and Environmental Monitoring Unit for the upgrade of production ATE Testers, putting the Pin Electronics into the Test Head for better performance while testing FPGAs. Design of the Electron Beam Blanker-Control System for Litho Mask Making equipment down to 1/4 nanosecond pulse, for 2 GHz Quality Control delivered to the E-BEAM blanker plates. Design of the Stimulus & Response electronics of a light-based process for controlling a Biotech chemical reaction.


PCB & ASIC designs in CMOS, ECL, GaAs
Clock Generation & distribution, PLL > 3 GHz
SPICE Simulations of Backplanes, PCBs & Devices
Teach customized high speed design rules for teams
PCB Fab Specs, routing rules, design reviews
Compliance Testing of High Speed Serial Paths
OrCAD Schematic Capture
Signal Integrity & Power Integrity Reviews
Very Fast architectures, data transfers, DACs & ADCs.
Very low jitter systems design & test.

Education and Background:
UC Davis
Bachelor of Science (BS) Engineering, Electrical and Electronics Engineering