RTL Coding
Verilog/VHDL
ASIC/FPGA
System Design
Chip Architecture
Signal Processing
Synthesis & Timing
Place & Route
Modeling
Simulations & Verification
Diagnostics
Chip/Board Bring-up
Design Reviews
IIR Digital Filter Design
Education and Background:
Stanford University
MSEE, Digital Systems Design
Cal Poly San Luis Obispo
BSEE, Electrical and Electronics Engineering